The present invention relates to a digital recorded data reproducing device which reproduces digital data recorded in a recording medium and, more particularly, to one having its phase-locked loop and offset correction improved, and to one which has reproduction digital data quality improved as well as playability enhanced under unfavorable conditions such as a deterioration in a reproduced waveform quality due to tilt, a reproduction on condition of bad signal-noise ratio, and a frequent occurrence of defect or the like.
As is generally known, a tilt represents a deviation of an angle made between a perpendicular standing on a signal surface of an optical disk and an optical axis of a laser beam, and a defect represents a disturbing factor to a reproduced waveform such as a scratch or a fingerprint adhesion on the signal surface of the optical disk.
A method of keeping a linear velocity constant to uniformize recording density on a recording medium is commonly employed as a method for recording digital data on an optical disk medium as seen in Compact Disk or DVD.
When digital data are reproduced based on a reproduction signal of an optical disk which is subjected to mark width modulation and to digital modulation recording so that linear recording density is constant, a phase-locked pull-in is conventionally performed by detecting a phase of a clock component held by the reproduction signal and constituting a phase-locked loop.
At the time, when the frequency of the clock component held by the reproduction signal and the frequency of a clock generated by the phase-locked loop differ vastly, it is likely that a phase-locked pull-in is not completed or that a pseudo pull-in to a different frequency is performed.
As a means for avoiding this problem, conventionally a reproduction linear velocity cycle is detected by a specified pulse length or pulse interval included in a reproduction signal and control of a disk rotation speed or of a free-running frequency of a phase-locked loop is performed, thereby enabling a normal phase-locked pull-in.
For example, there is a disk reproduction system as shown in FIG. 23. A digital recording code as shown in FIG. 24(a) is recorded on an optical disk 55 so that linear recording density is constant. Recorded data are supposed to be data regulated to have three to fourteen pieces of consecutive xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d as in 8-16 modulation system, for example. A signal obtained by a reproduction at a reproducing means 56 such as an optical pickup has its amplitude attenuated in a higher frequency component according to an increase in the recording density of the recorded data in a linear direction as shown in FIG. 24(a). This is because an effect of interference is significantly produced according to an increase in recording density, and thus, the signal obtained by reproduction is amplified by a preamplifier not shown and is subjected to correction which emphasizes a higher frequency component by a waveform equalizing means 2 thereafter.
A reproduction signal subjected to high frequency emphasis is sampled to a digital signal with multiple bits by an analog/digital converter 3 as a means for converting an analog signal to a digital signal as shown in FIG. 24(b). At this time, a reproduction clock generated by a VCO (voltage Control Type Oscillator) 40 is employed as a sampling clock, and when a phase of the reproduction clock by the VCO 40 and a phase of a clock component held by the reproduction signal by the reproducing means 56 are synchronized with each other, sampling data as shown in FIG. 24(c) are obtained.
FIG. 24(c) illustrates sampling data suitable particularly for Partial Response Maximum Likelihood (hereinafter, abbreviated as xe2x80x9cPRMLxe2x80x9d) signal processing system. The PRML signal processing system is one which requires no high frequency component in a reproduction signal by adding a waveform interference intentionally and enhances an error rate of reproduction data by using a maximum likelihood decoding method, which demodulates the most probable series by a probability calculation considering the waveform interference, together in a reproduction system in which an amplitude of a high frequency component of a signal deteriorates and a signal-noise ratio increases with an increase in recording density in a linear recording direction.
The sampled digital signal with multiple bits is inputted to an offset correction means 4 to correct an offset component included in the reproduction digital signal. The reproduction digital signal subjected to offset correction is inputted to a transversal filter 6 to perform a partial response equalization.
At this time, it is characteristic that an equalization output signal is multivalued by applying the partial response equalization as shown in FIG. 24(d). A weighting factor of a tap of the transverse filter 6 is supplied by a tap weighting factor setting means 57 for setting weighting factors employing Least Mean Square (hereinafter, referred to as xe2x80x9cLMSxe2x80x9d) algorithm which minimizes a mean square value of an equalization error. The multivalued output signal of the transversal filter 6 is demodulated by a viterbi decoder 58 as a kind of maximum likelihood decoder to obtain binary digital data.
A phase-locked reproduction clock used in sampling by the analog/digital converter 3 is controlled as follows. That is, a position where an output signal of the offset correction means 4 crosses zero level is successively detected from the output signal, a synchronization pattern length in a specified period over 1 frame is detected employing an output of a zero-cross length detector 59 which counts the sampling number between neighboring zero-crosses, and further a detection cycle of a synchronization pattern is detected by a frequency error detector 13, thereby deciding a frequency error amount to perform frequency control of the reproduction clock. Further, phase information of reproduction digital data is detected by a phase comparator 9 employing the output signal of the offset correction means 4, and a phase error amount to perform phase synchronizaiton control of the reproduction clock and the reproduction digital data is decided.
The VCO 40 is controlled by a loop filter 14 for frequency control and a digital/analog converter 42b employing the frequency error amount outputted from the frequency error detector 13 so as to control frequency to an area where the reproduction clock can be synchronized with the reproduction digital signal. Meanwhile, the VCO 40 is controlled by a loop filter 60 for phase control and a digital/analog converter 42a employing the phase error amount outputted from the phase comparator 9 so that the reproduction clock is synchronized with the reproduction digital signal. That is, the VCO 40 has outputs of the digital/analog converter 42a and the digital/analog converter 42b, which are added by an adder 61, inputted as its control input.
By a series of the operation, a phase of the reproduction clock and a phase of a clock component held by the reproduction digital data can be synchronized with each other, resulting in a stable and accurate reproduction of digital data recorded on an optical disk medium.
However, when a phase error detection as a part of the phase-locked loop is performed based on a signal before the partial response equalization processing as described above, phase error information is incorrect, and thus a jitter of the phase-locked loop increases, under such conditions as the deterioration in the reproduction signal due to tilt and insufficiencies of equalization characteristics of the waveform equalizing means. Thus, a signal sampled by the analog/digital converter is out of normal phase state, and therefore the performance cannot be sufficiently achieved in a partial response equalization by the transversal filter. Therefore, the quality of the reproduction signal is deteriorated and the deterioration in the error rate may be caused.
Further, though it is already proposed to perform a phase error detection based on the output signal of the transversal filter as a means for avoiding such state, it cannot be an effective avoidance means because a loop delay in the phase-locked loop is increased, and a range of phase-locked pull-in is decreased or the stability of the phase synchronization is lost according to the method.
The present invention is made to solve the above-mentioned problems and has for its object to provide a digital recorded data reproducing device which is most suitable for a partial response equalization, is high in phase-locked pull-in capacity, and is capable of decreasing an error rate even under such conditions as the characteristic deterioration due to tilt and insufficiencies of analog equalization.
According to claim 1 of the present invention, a digital recorded data reproducing device comprises: an analog/digital converting means for sampling a reproduction signal of a recording medium to digital data asynchronously with a phase of a clock component included in the signal; a digital data correction means for correcting an offset component and an amplitude from the sampled signal; an equalizing filter for subjecting the corrected signal to a partial response equalization; an interpolation filter for reproducing a signal in a regular sampling phase from the signal subjected to the partial response equalization by interpolation; a filter factor control means for adaptively controlling a filter factor of the equalizing filter so that an equalization error is minimum based on an output signal of the interpolation filter; a phase-locked loop for detecting a phase error based on the output signal of the interpolation filter to update a filter factor of the interpolation filter; and a maximum likelihood decoder for subjecting the output signal of the interpolation filter to a maximum likelihood decoding according to a type of partial response at equalization by the equalizing filter so as to perform a data demodulation.
Therefore, a maximum likelihood decoding can be performed based on interpolation data in a regular sampling phase, resulting in a digital data demodulation which is not affected by a waveform deterioration due to tilt of a reproduction signal or the like and is suitable for a partial response maximum likelihood decoding.
According to claim 2 of the present invention, a digital recording data reproducing comprises: an analog/digital converting means for sampling a reproduction signal of a recording medium to digital data asynchronously with a phase of a clock component included in the signal; a digital data correction means for correcting an offset component and an amplitude from the sampled signal; an equalizing filter for subjecting the corrected signal to a partial response equalization; a phase-locked loop for detecting a phase error based on an output signal of the equalizing filter; a filter factor control means for adaptively controlling a filter factor of the equalizing filter so that an equalization error is minimum based on the output signal of the equalizing filter as well as controlling the filter factor so that there is no phase error based on an output of the phase-locked loop; and a maximum likelihood decoder for performing a maximum likelihood decoding according to a type of partial response at equalization by the equalizing filter so as to perform a data demodulation.
Therefore, a maximum likelihood decoding can be performed based on interpolation data in a regular sampling phase, resulting in a digital data demodulation which is not affected by a waveform deterioration due to tilt of a reproduction signal or the like and is suitable for a partial response maximum likelihood decoding. Further, it is effective for reduction in circuit scale or cost, low power consumption, or decrease in an error rate.
According to claim 3 of the present invention, a digital recorded data reproducing device as defined in claim 1 or 2 comprises: a clock generating means for generating a clock with a phase asynchronous with that of a clock signal included in the reproduction signal of the recording medium; a frequency control means for controlling a frequency of the clock generated by the clock generating means based on the output of the phase-locked loop; and a phase synchronization maintaining means for performing a control so that a phase of the clock generated by the clock generating means maintains a synchronization state based on the output of the phase-locked loop.
Therefore, an oscillation control of the clock generating means can be performed only by a rough frequency control and an up/down control in the neighborhood of synchronization frequency, resulting in a phase-locked loop with high accuracy as well as in drastic reduction in analog elements. Further, there is no need to perform a high frequency operation, thereby requiring no measures against noise generation.
According to claim 4 of the present invention, a digital recorded data reproducing device as define in claims 3 comprises: a delta/sigma modulating means for subjecting control signals from the frequency control means and the phase synchronization maintaining means to a delta/sigma modulation; and a low pass filter for removing a high frequency component of an output signal of the delta/sigma modulating means.
Therefore, a disturbance in a phase-locked loop when a rough control is switched to an up/down control can be suppressed and a smooth frequency followup can be performed, whereby a more stable phase-locked pull-in can be realized, resulting in an enhancement in error rate of reproduction data. Further, a control of the clock generating means may also be designed in consideration mainly of an enhancement in control performance of the rough control, thereby simplifying an analog circuit.
According to claim 5 of the present invention, a digital recorded data reproducing device as defined in claim 4 comprises a time constant varying means for varying a time constant of the low pass filter.
Therefore, when a reproduction speed of a recording medium is changed, a time constant can be varied according to the speed, whereby a smooth frequency followup can be performed independently of the reproduction speed in a data reproduction system which has a mode of reproducing the recording medium at double speed.
According to claim 6 of the present invention, in a digital recorded data reproducing device as defined in claim 1 or 2, when an offset adjustment is performed, the digital data correction means adds an amplitude component of a point where a center line of a sampled waveform crosses zero level with respect to the point, while the means adds a prescribed value according to a polarity of a reproduction code with respect to the other points where a code is decided.
Therefore, an accuracy of offset error information increases, and even when an offset adjustment is made to respond to a direct current fluctuation including a high frequency component, a stabilization of the operation and decrease in noise after adjustment are possible, whereby a data reproducing means available for the direct current fluctuation can be realized.
According to claim 7 of the present invention, in a digital recorded data reproducing device as defined in claim 1 or 2, when an offset adjustment is performed, the digital data correction means adds an amplitude component of a point where a center line of a sampled waveform crosses zero level with respect to the point, while the means adds a value according to a polarity of a reproduction code with respect to the other points where a code is decided, and makes the additional value different between at seek operation and at the other time.
Therefore, an accuracy of offset error information increases, and, even when an offset adjustment is made to respond to a direct current fluctuation including a high frequency component, a stabilization of the operation and a decrease in noise after adjustment are possible, whereby a data reproducing means available for the direct current fluctuation can be realized, and a control according to an operating state is possible, thereby enhancing a playability.
According to claim 8 of the present invention, in a digital recorded data reproducing device as defined in claim 7, the digital data correction means increases the additional value at seek operation while the means decreases the additional value in a phase synchronization state.
Therefore, it is possible to increase a followup property during seek operation and to suppress control noise in a phase synchronization state, thereby enabling the most suitable offset control.
According to claim 9 of the present invention, in a digital recorded data reproducing device as defined in claim 1 or 2, when an offset adjustment is performed, the digital data correction means monitors a cumulative additional value for a prescribed period of time at each point in a sampled waveform and gives feedback of an error amount for a direct current part discretely to the direct current part.
Therefore, it is possible to perform a restoration from a pseudo lock state as an abnormal state at high speed, thereby enhancing a playability.
According to claim 10 of the present invention, in a digital recorded data reproducing device as defined in claim 2, after performing a phase-locked pull-in, the filter factor control means performs a partial response equalization successively as well as sets its loop gain to be sufficiently low as compared with the phase-locked loop, and performs a switching to an intermittent control operation when the phase error is decreased.
Therefore, quality of attitude data is increased, thereby enhancing a speed of phase-locked pull in.
According to claim 11 of the present invention, in a digital recorded data reproducing device comprising: a preamplifier for emphasizing an output amplitude of a reproduction signal from a recording medium; a waveform equalizing means for emphasizing a prescribed frequency band of the emphasized signal; an analog/digital converting means for sampling the equalized signal to a digital data with multiple bits asynchronously with a phase of a clock component included in the signal by a clock generated by an oscillator; an offset correction means for decreasing an offset component from the sampled signal; an automatic gain control means for adjusting the amplitude of the output signal to a required level; a transversal filter for subjecting the signal subjected to the amplitude adjustment to a partial response equalization; a high-order interpolation filter for reproducing a signal in a regular sampling phase from the signal subjected to the partial response equalization by a high-order interpolation; a tap weighting factor control means for controlling a tap weighting factor of the transversal filter from the interpolation output signal adaptively so that an equalization error is minimum; a phase comparator for detecting a phase error from the interpolation output signal; a loop filter for smoothing the phase error signal; and a maximum likelihood decoder for subjecting the interpolation output signal to a maximum likelihood decoding according to a type of partial response at equalization by the transversal filter so as to perform a data demodulation, the asynchronously sampled signal is subjected to the partial response equalization, and a phase synchronization is compensated by a phase-interpolation-type digital phase-locked loop so that a data demodulation is performed.
Therefore, even under such conditions as a characteristic deterioration of a reproduction signal due to tilt and insufficiencies of analog equalization, it is possible to decrease a jitter in a phase-locked loop as well as to reproduce the most suitable partial response equalization signal by detecting phase error information after partial response equalization, thereby enabling a stable digital data reproduction which reduces an error rate as well as has high phase-locked pull-in capacity.
According to claim 12 of the present invention, in a digital recorded data reproducing device comprising: a preamplifier for emphasizing an output amplitude of a reproduction signal from a recording medium; a waveform equalizing means for emphasizing a prescribed frequency band of the emphasized signal; an analog/digital converting means for sampling the equalized signal to a digital data with multiple bits asynchronously with a phase of a clock component included in the signal by a clock generated by an oscillator; an offset correction means for decreasing an offset component from the sampled signal; an automatic gain control means for adjusting the amplitude of the output signal to a required levels a phase-interpolation-type transversal filter, which has functions of a transversal filter and a high-order interpolation filter together, for subjecting the signal subjected to the amplitude adjustment to a partial response equalization and reproducing a signal in a regular sampling phase from the signal subjected to the partial response equalization by a high-order interpolation; a phase comparator for detecting a phase error from the output signal; a loop filter for smoothing the phase error signal to obtain phase information; a tap weighting factor setting means for setting a weighting factor of a tap of the phase-interpolation-type transversal filter which makes an equalization error minimum and is for reproducing a normal sampling signal from the phase information and the output signal of the phase-interpolation-type transversal filter; and a maximum likelihood decoder for subjecting the interpolation output signal to a maximum likelihood decoding according to a type of partial response at equalization by the phase-interpolation-type transversal filter so as to perform a data demodulation, the partial response equalization and a digital phase-locked loop are realized by the same filter.
Therefore, a transversal filter and a high-order interpolation filter, which are supposed to be large in circuit scale, can be communized only by the transversal filter, thereby realizing reduction in circuit scale and particularly low power consumption at high speed reproduction.
According to claim 13 of the present invention, in a digital recorded data reproducing device as defined in claim 12, the tap weighting factor setting means has a filter factor for each phase which is divided in a phase direction, updates the filter factor for phase control according to the phase information outputted from the loop filter, updates a filter factor for partial response equalization so as to minimize the equalization error based on the output signal of the phase-interpolation-type transversal filter, and superimposes the filter factor for phase control and the filter factor for partial response equalization, thereby setting the weighting factor of a tap of the phase-interpolation-type transversal filter.
Therefore, a means for setting a filter factor for phase control and a means for setting a tap weighting factor for partial response equalization can be operated individually, whereby even when a partial response equalization and a data interpolation in a regular phase are communized only by the phase-interpolation-type transversal filter, an effective control with high accuracy is possible without losing both characteristics.
According to claim 14 of the present invention, in a digital recorded data reproducing device as defined in claim 12, the tap weighting factor setting means comprises: a temporary judging circuit for detecting an equalization target value which corresponds to partial response system based on the output signal of the transversal filter; an equalization error detector for detecting the equalization error based on the equalization target value and the output signal of the high-order interpolation filter; a correlator for detecting correlation between the equalization error and the output signal of the high-order interpolation filter; a feedback gain regulator for multiplying an output of the correlator by the same number as a gain to regulate a feedback gain; a tap factor updating part for adding an output of the feedback gain regulator to a weighting factor of each tap to update a tap factor; a first register for storing each amplitude value when a channel rate of Nyquist characteristics is divided in a time direction correspondingly to each tap; a tap factor folding means for superimposing each tap stored in the first register as well as a Nyquist interpolation factor in each phase and a tap weighting factor for partial response equalization which factor is outputted from the tap factor updating part; plural delay elements having delay amount of unit delay time, to which of the first stage the signal subjected to the partial response equalization is inputted and which are interconnected in series; an multiplier which is set correspondingly to an input of the delay element in the first stage among the plural unit delay elements as well as outputs of a connection point between delay elements and of a delay element in the last stage; an adder for obtaining the sum total of outputs of the multiplier to generate an output of the tap weighting factor setting means; a second register which is set correspondingly to the multiplier; a register value updating means for updating a value of the second register based on an output of the tap factor folding means; and a selector which is set according to the second register and selects an amplitude value stored in the second register to output to the corresponding multiplier, according to the output phase information of the loop filter.
Therefore, there is provided a specific constitution for realizing a tap factor folding which enables an effective control with high accuracy without losing both characteristics even when a partial response equalization and a data interpolation in a regular phase are communized only by the phase-interpolation-type transversal filter.
According to claim 15 of the present invention, in a digital recorded data reproducing device as defined in claim 12 comprising: a frequency error detector for detecting a frequency error from the output of the traversal filter; and a loop filter for frequency control for smoothing the detected frequency error and giving the same to the oscillator as a control signal, a gain of a loop for frequency control which includes the loop filter for frequency control is reduced in a state where the frequency error is under a prescribed value, so that the processing shifts from a frequency pull-in control to a phase-locked pull-in control, a loop gain of a loop for phase control which includes the phase comparator is reduced in a case where the prescribed number of synchronization pattern is detected, so that the processing shifts to a partial response adaptive automatic equalization control by the phase-interpolation-type tap weighting factor control means, and the processing shifts to an interval-control-type partial response adaptive automatic equalization control which discretely reflects a cumulative additional value of an equalization error amount on a tap weighting factor in a state where an equalization error by the partial response adaptive automatic equalization control is under a prescribed value.
Therefore, it is possible to realize a stable phase-locked loop and to prevent a state out of control after the processing shifts from a rough control to a phase synchronization state.
According to claim 16 of the present invention, in a digital recorded data reproducing device as defined in claim 12, the tap weighting factor setting means sets a feedback gain when the filter factor for phase control is updated so as to be sufficiently larger than a feedback gain when the filter factor for the partial response equalization is updated, and updates the filter factor for the partial response equalization discretely.
Therefore, a competition between a control of a filter factor for phase control and a control of a tap weighting factor for partial response equalization are prevented, and a phase control is given priority to, thereby realizing a stable phase-locked loop as well as enhancing a playability because an accuracy of a partial response equalization is not lost, and an out-of-control state does not occur against an abnormal signal.
According to claim 17 of the present invention, a digital recorded data reproducing device comprises: a preamplifier for emphasizing an output amplitude of a reproduction signal from a recording medium; a waveform equalizing means for emphasizing a prescribed frequency band of the emphasized signal; an analog/digital converting means for sampling the equalized signal to a digital data with multiple bits asynchronously with a phase of a clock component included in the signal by a clock generated by an oscillator; an offset correction means for decreasing an offset component from the sampled signal; an automatic gain control means for adjusting the amplitude of the output signal to a required level; a transversal filter for subjecting the signal subjected to the amplitude adjustment to a partial response equalization; a high-order interpolation filter for reproducing a signal in a regular sampling phase from the signal subjected to the partial response equalization by a high-order interpolation; a tap weighting factor control means for controlling a tap weighting factor of the transversal filter from the interpolation output signal adaptively so that an equalization error is minimum; a phase comparator for detecting a phase error from the interpolation output signal; and a loop filter for smoothing the phase error signal; and a maximum likelihood decoder for subjecting the interpolation output signal to a maximum likelihood decoding according to a type of partial response at equalization by the transversal filter so as to perform a data demodulation, as well as comprises: a frequency control means for performing a control based on a cycle of a synchronization pattern included in recording data and a time width with which the synchronization pattern is detected; a phase synchronization maintaining means for monitoring a control range of the loop filter after a frequency and a frequency of a clock component included in the reproduction signal are pulled in to the neighborhood and performing an up/down control of a clock frequency so that the phase control signal returns to a normal operating range before the signal reaches an area out of phase synchronization control; and an oscillator control means for controlling the oscillator based on an output signal of the frequency control means and an output signal of the phase synchronization maintaining means.
Therefore, a frequency of an asynchronous clock at reproduction signal sampling can be always maintained within a controllable range of a digital phase-locked loop. Thereby, a smooth digital recorded data reproduction is possible with no discontinuity point occurring at phase synchronization control, and a frequency control and a phase control can be thought separately, resulting in a simple constitution of the control means of an oscillator.
According to claim 18 of the present invention, in a digital recorded data reproducing device as defined in claim 17, the oscillator control means comprises: a delta/sigma modulator for modulating the control signal at up/down control by the phase synchronization maintaining means; and a low pass filter for smoothing the output signal, thereby to control the oscillator by the output signal.
Therefore, in a case where a minimum frequency control resolution of an oscillator is rough, and an oscillation frequency varies vastly at up/down control when a frequency of an asynchronous clock employed for reproduction signal sampling is maintained within a controllable range of a digital phase-locked loop, a modulation is performed in a time direction to control an oscillation frequency of the oscillator with finer resolution than original, whereby there is no disturbance at up/down and a successive reproduction is possible, though there is a risk of disturbance generation in the phase-locked loop, and thus reproduction quality is enhanced.
According to claim 19 of the present invention, a digital recorded data reproducing device as defined in claim 18 further comprises a cut-off frequency varying means for switching a cut-off frequency of the low pass filter according to a reproduction speed of digital recording data.
Therefore, in a case where plural reproduction speeds have to be compensated, or there is a difference between the inner and outer peripheries as well as in a kind of recording medium, so that a broad range of frequency control band is provided when digital recording data are reproduced, response characteristics suitable for each reproduction speed can be realized, whereby reproduction characteristics can be maintained even under the condition that a reproduction speed changes vastly.
According to claim 20 of the present invention, in a digital recorded data reproducing device as defined in any of claims 11, 12, and 17, the offset correction means comprises: an offset detecting means for detecting an offset component held by the sampled signal; a smoothing means for smoothing the detected offset component; and a subtracting means for subtracting the smoothed signal from the sampled signal.
Therefore, the configuration to perform an offset correction can be realized in a device which is capable of performing a stable digital data reproduction that reduces an error rate as well as has high phase-locked pull-in capacity even under such conditions as a characteristic deterioration of a reproduction signal due to tilt and insufficiencies of analog equalization.
According to claim 21 of the present invention, in a digital recorded data reproducing device which comprises: a preamplifier for emphasizing an output amplitude of a reproduction signal from a recording medium; a waveform equalizing means for emphasizing a prescribed frequency band of the emphasized signal; an analog/digital converting means for sampling the equalized signal to a digital data with multiple bits asynchronously with a phase of a clock component included in the signal by a clock generated by an oscillator; an offset correction means for decreasing an offset component from the sampled signal; an automatic gain control means for adjusting the amplitude of the output signal to a required level; a transversal filter for subjecting the signal subjected to the amplitude adjustment to a partial response equalization; a high-order interpolation filter for reproducing a signal in a regulars sampling phase from the signal subjected to the partial response equalization by a high-order interpolation; a tap weighting factor control means for controlling a tap weighting factor of the transversal filter from the interpolation output signal adaptively so that an equalization error is minimum; a phase comparator for detecting a phase error from the interpolation output signal; a loop filter for smoothing the phase error signal; and a maximum likelihood decoder for subjecting the interpolation output signal to a maximum likelihood decoding according to a type of partial response at equalization by the transversal filter so as to perform a data demodulation, the asynchronously sampled signal is subjected to the partial response equalization, and a phase synchronization is compensated by a phase-interpolation-type digital phase-locked loop so that a data demodulation is performed, as well as the offset correction means performs an offset correction with reference to the output of the high-order interpolation filter.
Therefore, an offset detection with higher accuracy than an offset correction only by a polarity of a reproduction signal code can be performed, whereby control noise after offset correction is reduced and a larger feedback gain can be set. Thereby, it is possible to follow a level fluctuation having a higher frequency component, resulting in an enhancement in playability even at reproduction under an abnormal condition such as a defect.
According to claim 22 of the present invention, in a digital recorded data reproducing device as defined in claim 21, the offset correction means comprises: a zero-cross amplitude output means for outputting a component in an amplitude direction with respect to a sampling signal at a position where the output signal of the high-order interpolation filter crosses zero; a polarity value output means for outputting a certain amount of values with different polarity according to a polarity of the signal code with respect to a sampling signal at a position other than the zero-cross position; a loop filter for offset correction for smoothing the output signal of the zero-cross amplitude output means and the output signal of the polarity value output means; and an offset removing means for performing an offset removal by directly subtracting the output signal from the output signal of the analog/digital converter.
Therefore, an offset correction according to a recording medium is possible even when a different recording medium is reproduced.
According to claim 23 of the present invention, in a digital recorded data reproducing device as defined in claim 22, the offset correction means comprises: a polarity value output varying means for varying the output value of the polarity value output means to adjust a ratio of the same to the output value of the zero-cross amplitude output means.
Therefore, the most suitable offset correction according to such states that a control is performed mainly for a code polarity at seek when a followup property to a level fluctuation is required more than accuracy of a reproduction signal, while a control is performed mainly for a zero-cross amplitude at reproduction of successive data when accuracy of a reproduction signal is required, is possible, and further, it involves convergency of control, thereby enabling a high speed phase-locked pull-in after seek.
According to claim 24 of the present invention, in a digital recorded data reproducing device as defined in claim 22, the offset correction means comprises an output value switching means for switching an output value according to an operating state of the digital recorded data reproducing device, by making the output value of the polarity value output means larger than the output value of the zero-cross amplitude output means at seek, and making the output value of the polarity value output means smaller than the output value of the zero-cross amplitude output means at successive data reproduction.
Therefore, a generation of a quasi-phase synchronization is avoided, and, even when the quasi-phase synchronization is generated under certain conditions, an early self-restoring is possible, thereby enhancing playability.
According to claim 25 of the present invention, in a digital recorded data reproducing device as defined in claim 22, the offset correction means comprises: a counter for counting a certain period of time; a cumulative adding means for cumulatively adding the output value of the polarity value output means and the output value of the zero-cross amplitude output means between flags outputted from the counter; and a cumulative adding result monitoring means for monitoring the output signal of the cumulative adding means at a timing of the flag where the output signal is outputted from the counter, and, when being judged as a quasi-phase synchronization state, performing a switching to a control in which a ratio of the polarity value output means is high, so as to restore the state to a normal synchronization state.
Therefore, the configuration to perform an offset correction can be realized in a device which is capable of performing a stable digital data reproduction that reduces an error rate as well as has high phase-locked pull-in capacity even under such conditions as a characteristic deterioration of a reproduction signal due to tilt and insufficiencies of analog equalization.
According to claim 26 of the present invention, in a digital recorded data reproducing device as defined in any of claims 11, 12, 17, and 21, the transversal filter comprises: plural delay elements having delay amount of unit delay time, to which of the first stage the signal subjected to the amplitude adjustment is inputted and which are interconnected in series; an multiplier which is set correspondingly to an input of the delay element of the first stage among the plural unit delay elements as well as outputs of a connection point between delay elements and of a delay element of the last stage; an adder for obtaining the sum total of outputs of the multiplier to generate an output of the filter, wherein a weighting factor inputted to the other input of the multiplier is varied, thereby to realize required equalization characteristics.
Therefore, the configuration to perform a partial response equalization can be realized in a device which is capable of performing a stable digital data reproduction that reduces an error rate as well as has high phase-locked pull-in capacity even under such conditions as a characteristic deterioration of a reproduction signal due to tilt and insufficiencies of analog equalization.
According to claim 27 of the present invention, in a digital recorded data reproducing device as defined in any of claims 11, 17, and 21, the high-order interpolation filter comprises: plural delay elements having delay amount of unit delay time, to which of the first stage the signal subjected to the partial response equalization is inputted and which are interconnected in series; an multiplier which is set correspondingly to an input of the delay element in the first stage among the plural unit delay elements as well as outputs of a connection point between delay elements and of a delay element in the last stage; an adder for obtaining the sum total of outputs of the multiplier to generate an output of the filter, wherein a weighting factor inputted to the other input of the multiplier is varied, thereby to realize required equalization characteristics.
Therefore, the configuration to interpolate a signal in a regular sampling phase can be realized in a device which is capable of performing a stable digital data reproduction that reduces an error rate as well as has high phase-locked pull-in capacity even under such conditions as a characteristic deterioration of a reproduction signal due to tilt and insufficiencies of analog equalization.
According to claim 28 of the present invention, in a digital recorded data reproducing device as defined in claim 27, the high-order interpolation filter performs an interpolation base on Nyquist characteristics.
Therefore, the configuration to interpolate a signal in a regular sampling phase can be realized in a device which is capable of performing a stable digital data reproduction that reduces an error rate as well as has high phase-locked pull-in capacity even under such conditions as a characteristic deterioration of a reproduction signal due to tilt and insufficiencies of analog equalization.
According to claim 29 of the present invention, in a digital recorded data reproducing device as defined in claim 27, the high-order interpolation filter comprises: a register which is set correspondingly to the multiplier and stores each amplitude value when a channel rate of Nyquist characteristics is divided in a time direction; and a selector which is set correspondingly to the register and selects the amplitude value stored in the register to output to the corresponding multiplier according to the output phase information of the loop filter.
Therefore, the configuration to interpolate a signal in a regular sampling phase can be realized in a device which is capable of performing a stable digital data reproduction that reduces an error rate as well as has high phase-locked pull-in capacity even under such conditions as a characteristic deterioration of a reproduction signal due to tilt and insufficiencies of analog equalization.
According to claim 30 of the present invention, in a digital recorded data reproducing device as defined in any of claims 11, 17, and 21, the tap weighting factor control means decides the weighting factor of the transversal filter by Least Mean Square algorithm.
Therefore, the configuration to set a weighting factor so as to realize a function of partial response equalization which should be performed by a transversal filter can be realized in a device which is capable of performing a stable digital data reproduction that reduces an error rate as well as has high phase-locked pull-in capacity even under such conditions as a characteristic deterioration of a reproduction signal due to tilt and insufficiencies of analog equalization.
According to claim 31 of the present invention, in a digital recorded data reproducing device as defined in claim 30, the tap weighting factor control means comprises: a temporary judging circuit for detecting an equalization target value which corresponds to a partial response system based on the output signal of the high-order interpolation filter; an equalization error detector for detecting the equalization error based on the equalization target value and the output signal of the high-order interpolation filter; a correlator for detecting correlation between the equalization error and the output signal of the high-order interpolation filter; a feedback gain regulator for multiplying an output of the correlator by the same number as a gain to regulate a feedback gain; and a tap factor updating part for adding an output of the feedback gain regulator to a weighting factor of each tap to update a tap factor.
Therefore, the configuration to set a weighting factor so as to realize a function of partial response equalization which should be performed by a transversal filter can be realized in a device which is capable of performing a stable digital data reproduction that reduces an error rate as well as has high phase-locked pull-in capacity even under such conditions as a characteristic deterioration of a reproduction signal due to tilt insufficiencies of analog equalization.
According to claim 32 of the present invention, in a digital recorded data reproducing device as defined in claim 15, the frequency error detector comprises: a zero-cross length detector for detecting an interval at which the output signal of the high-order interpolation filter crosses zero level; a synchronization pattern length detector for detecting whether a ratio of neighboring zero-cross lengths coincides with a prescribed synchronization pattern length on the basis of the ratio or not to obtain first cycle information which reflects a reproduction speed of the recording medium; and a synchronization pattern interval detector for detecting an interval until the synchronization pattern is detected to detect second cycle information based on this and a prescribed period.
Therefore, the configuration to detect a frequency error can be realized in a device which is capable of realizing a stable phase-locked loop and preventing a state out of control after the processing shifts from a rough control to a phase synchronization state.